Lesson 1 of 5
Inside the CPU: Registers and the Fetch–Decode–Execute Cycle
Trace a single instruction through the MAR, MDR, PC, CIR and ALU — the way real processors do it.
Learn it
A CPU does not 'know' a program. It just repeats one loop billions of times per second: fetch an instruction, work out what it means, then do it.
To do that it uses tiny ultra-fast boxes called registers. The Program Counter (PC) remembers which instruction is next, and the Accumulator holds the number currently being worked on.
Speeding this loop up is why clock speed, cores and pipelining exist.
Key terms
- MAR
- Memory Address Register — holds the address of the memory location currently being read from or written to.
- MDR
- Memory Data Register — holds the data or instruction that has just been fetched from, or is about to be written to, memory.
- CIR
- Current Instruction Register — holds the instruction currently being decoded and executed.
- Pipelining
- Overlapping the fetch, decode and execute stages of consecutive instructions to increase throughput.
One full cycle, step by step
Follow the instruction stored at address 12 all the way through the processor.
- 11. Address out: The value in the PC (12) is copied into the MAR and placed on the address bus.
- 22. Fetch: Memory returns the contents of address 12 on the data bus into the MDR.
- 33. Increment: The PC is incremented to 13 so the next fetch is ready — this happens before execution, which is why jumps must overwrite the PC.
- 44. Decode: The MDR contents move to the CIR; the control unit splits the word into opcode and operand.
- 55. Execute: The ALU performs the operation and stores the result in the accumulator, setting status flags such as zero and carry.
Try it
Put one fetch–decode–execute cycle back into the correct hardware order.
- 1Copy MDR into the CIR
- 2ALU executes and updates the accumulator and flags
- 3Increment the PC
- 4Copy PC into MAR
- 5Control unit decodes opcode and operand
- 6Memory places the instruction on the data bus into the MDR
Challenge
A 3.2 GHz CPU has a 5-stage pipeline. A program of 1,000,000 instructions runs with no stalls. Roughly how long does it take, and how much longer would it take with no pipelining at all (5 cycles per instruction)?
Pick whichever way suits you — every mode earns the same bonus XP.
Write at least 40 more characters to submit.
Mark your own work
Guided walkthrough — 0/5 clues revealed
- Clue 1 locked — reveal it only if you get stuck.
- Clue 2 locked — reveal it only if you get stuck.
- Clue 3 locked — reveal it only if you get stuck.
- Clue 4 locked — reveal it only if you get stuck.
- Clue 5 locked — reveal it only if you get stuck.
Each clue costs 6 XP (never below 30 XP). You'd earn 60 XP right now.
Extension: Now assume 12% of instructions are branches and each mispredict wastes 4 cycles with 75% prediction accuracy. Recalculate.